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Allwinner /D1H /UART[0] /RXDMA_IE

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Interpret as RXDMA_IE

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (limit_done)limit_done 0 (blk_done)blk_done 0 (timeout_done)timeout_done 0 (buffer_overrun)buffer_overrun

Description

UART RXDMA Interrupt Enable Register

Fields

limit_done
blk_done
timeout_done
buffer_overrun

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data